About
I’m an Electrical Engineering graduate student at Arizona State University specializing in embedded systems, hardware validation, and FPGA/ASIC design.
I build real-world systems that combine low-level hardware, firmware, and intelligent edge computing: from automotive communication debugging to ML deployment on microcontrollers.
I’m currently seeking full-time roles in embedded systems, hardware validation, and firmware engineering.
Skills
Education
Master of Science in Engineering in Electrical Engineering
Arizona State University | Tempe | AZ | USA
Aug 2024 – May 2026
Coursework:
- EEE 591: Machine Learning Basics with Deployment to FPGAs
- EEE 518 Fund of Semiconductor Pack
- EEE 590 Reading and Conference
- EEE 525 VLSI Design
- EEE 591 Python for Rapid Engineering Solutions
- EEE 591 Communication Networks
- EEE 598 Topic: Advanced Hardware and Systems for Machine Learning
- EEE 598 Topic: Co-Design & Modelling/Adv Semiconductor Packaging
- CEN 598 Topic: Embedded Machine Learning
- EEE 598 Topic: Adv Electronics Packgng & Integrtd Processes/Tools
Bachelor of Technology in Electronics and Communication Engineering
PES University
Aug 2019 – Oct 2023
Coursework:
- Network Analysis and Synthesis, Digital Design Fundamentals, Embedded Systems, Hardware Security, Verification & Testing, Signal Processing, MATLAB
Minors: Computer Science Engineering
Work Experience
Associate Software Engineer
Jan 2024 – Jun 2024 | Tech Stack: STM32 • Embedded C • AUTOSAR • CAN • Renesas E1 • CANoe • CANalyzer • ECU-TEST
Worked on embedded firmware and validation for automotive ECUs, focusing on debugging, communication reliability, and system-level testing.
Debugged AUTOSAR-based firmware on STM32, improving system stability and reducing firmware update failures by 30%Implemented interrupt-driven CAN communication (filters, FIFO, mailboxes), increasing EOL regression pass rate from 85% → 98%
Streamlined flashing and validation workflows using Renesas E1 debugger, reducing deployment time by 30%
Diagnosed communication issues across 4+ ECU variants, improving message reliability and validation throughput
Student Trainee
Bosch Global Software Technologies | Bengaluru | KA | India
Feb 2023 – May 2023 | Tech Stack: STM32 • Embedded C • CAN • CANoe • CANalyzer • Debugging
Focused on embedded validation and CAN-based system debugging in automotive test environments.
Executed 50+ integration and CAN validation cycles, identifying timing mismatches and reducing recurring faults
Improved validation efficiency by ~40% by optimizing relay-box test setup
Debugged register-level configurations and baud-rate mismatches, restoring stable communication
Project Trainee
Bosch Global Software Technologies | Bengaluru | KA | India
Jun 2022 – Jul 2022 | Tech Stack: Embedded C • CAN • Hardware Validation • Sensor Systems
Supported early-stage hardware validation and embedded system testing
Validated sensor and ECU hardware across 30+ test runs, improving system reliability
Optimized test workflows, increasing execution efficiency by 30%
Other Experience
Graduate Service Assistant - Grader (Arizona State University)
Grader for EEE 405/591 ML with deployment with HDL to FPGA under Prof. Olin Hartin | Aug 2025- May 2026 | Tech Stack: Python, PyTorch, NumPy, SystemVerilog/Verilog, FPGA workflows, RTL Design, ML algorithms Tech
Graded 8+ technical homework assignments across two semesters for 40+ undergraduate and graduate students, covering machine learning theory, mathematical derivations, and implementation.
Evaluated Python and PyTorch-based implementations of ML algorithms including regression, classification, optimization methods, and neuralnetwork models.
Assessed student solutions involving hardware-oriented deployment of ML models using HDL concepts (Verilog/SystemVerilog) and FPGA-based acceleration workflows.
Reviewed algorithm correctness, numerical implementation, and computational efficiency when mapping ML models to digital hardware architectures.
Provided detailed technical feedback to reinforce ML fundamentals, hardware-aware model design, and practical deployment considerations.
Collaborated with the instructor to maintain grading consistency and ensure fair evaluation across assignments involving software and hardware design concepts.
Graduate Service Assistant - Grader (Arizona State University)
Grader for EEE 334: Circuits II under Prof. Olin Hartin | May 2025-Jul 2025| Tech Stack: LTSpice, Oscilloscope, Analog Discovery Kit, Multimeter, Analog Circuit Design, MOSFETs, Op-Amps
Graded lab reports and post-lab analyses for 90+ students in a junior-level analog electronics course focused on circuit design and experimental validation.
Evaluated experiments involving op-amp configurations (inverting, non-inverting, integrator, differentiator), diode circuits (rectifiers, clippers, clampers, voltage multipliers), and MOSFET parameter extraction.
Assessed frequency response and gain-bandwidth analysis of MOS amplifiers (CS, CG, CD) using theoretical calculations, simulation, and hardware measurements.
Verified student implementations using LTSpice simulations (AC, DC sweep, transient) and compared results with lab measurements from oscilloscopes, Analog Discovery Kit instrumentation, and handheld multimeters.
Reviewed percent-error analysis between theoretical, simulated, and experimental results to ensure technical accuracy and correct circuit interpretation.
Provided structured rubric-based feedback to support student understanding while maintaining grading consistency and FERPA compliance.